M27V322 Datasheet, PDF (4/13 Pages) STMicroelectronics – 32 Mbit 2Mb x16 Low Voltage UV EPROM and OTP EPROM

M27V322
Table 5. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
High Speed
≤ 10ns
0 to 3V
1.5V
Standard
≤ 20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
0V
Standard
2.4V
0.4V
1.5V
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
CL
OUT
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance ⁽¹⁾ (T_A = 25 °C, f = 1 MHz)
Symbol
Parameter
Test Condition
C_IN
Input Capacitance
V_IN = 0V
C_OUT
Output Capacitance
V_OUT = 0V
Note: 1. Sampled only, not 100% tested.
Min
Max
Unit
10
pF
12
pF
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between V_CC
and V_SS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween V_CC and V_SS for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
4/13