L6393 Datasheet, PDF (4/20 Pages) STMicroelectronics – Half-bridge gate driver

Pin connection
2
Pin connection
Figure 2. Pin connection (top view)
PHASE
1
SD
2
BRAKE
3
VCC
4
DT
5
CPOUT
6
GND
7
14
BOOT
13
HVG
12
OUT
11
NC
10
LVG
9
CP+
8
CP-
L6393
2.1
Pin description
Table 2.
Pin N#
Pin description
Pin name
Type
Function
1
PHASE
2
SD ⁽¹⁾
3
BRAKE
4
VCC
5
DT
6
CPOUT
7
GND
8
CP-
9
CP+
10
LVG ⁽¹⁾
11
NC
12
OUT
13
HVG ⁽¹⁾
14
BOOT
I
Driver logic input (active high)
I
Shut down input (active low)
I
Driver logic input (active low)
P
Lower section supply voltage
I
Dead time setting
O
Comparator output (open drain)
P
Ground
I
Comparator negative input
I
Comparator positive input
O
Low side driver output
Not connected
P
High side (floating) common voltage
O
High side driver output
P
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with V_CC > 3 V. This
allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
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