EMIF02-600FU7 Datasheet, PDF (4/9 Pages) STMicroelectronics – 10-BIT WIDE EMI FILTER INCUDINGESD PROTECTION

EMIF02-600FU7
ESD PROTECTION
In addition to its filtering function, the EMIF02-600FU7 is particularly optimized to perform ESD protection.
ESD protection is based on voltage clamping which can be calculated by :
V_CL = V_BR + R_d.I_PP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage Vout very low.
Fig A3 : ESD clamping behavior
Rg
R
ESD
Surge
Vg
Rd
Vin
Vbr
Rd
Vout
Vbr
Rload
S1
S2
EMIF02-600FU7
Device to be protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, R_G>>Rd and Rload>>Rd, it gives these
formulas:
Vin
=
Rg.Vbr+Rd.Vg
Rg
Vout
=
R.Vbr+Rd.Vin
R
The results of the calculation done for V_G=8kV, R_G=330Ω (IEC1000-4-2 standard) and V_BR=7V (typ.) give:
Vin = 20.33 V
Vout = 7.01 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to V_BR
Fig A4 : Measurement conditions
LOW-PASS FILTER
Vin
Vout
GND
GND
GND
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