AN1336 Datasheet, PDF (4/10 Pages) STMicroelectronics – Power-fail comparator for NVRAM supervisory devices

PFI/PFO operation in a system (how does it
work?)
AN1336
2
PFI/PFO operation in a system (how does it work?)
Figure 5: PFI/PFO in a typical system
9V
AC in
120/240V ^{AC VUNREG}
50/60HZ
5V
Regulator
VIN VCC
R1
VPFI
R2
M41ST85W
VCC VOUT
RST
PFO
INT
PFI
ECON
MCU
VCC
RST
NMI
INT
SRAM
VCC
W
G
E
AI04220
A typical power failure can be described by the following three events (see Figure 6:
"Power failure sequence"):
1. PFI triggered (t₀): As V_UNREG falls below the V_PFI threshold, PFO is asserted on the
MCU’s Non-Maskable Interrupt (NMI) pin. When NMI is asserted, the MCU halts its
current task and begins saving critical data to the NVRAM (safeguard routine).
2. V_CC begins to fall (t₁): the MCU will continue functioning until the safeguard routine is
complete or RESET occurs.
3. RESET asserted and/or Write Protect occurs (t₂):
At this point, the MCU needs to have completed the safeguard routine. This results in a
safeguard window from PFI to RESET /Write Protect (t₂ - t₀).
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