STV82X6 Datasheet, PDF (39/95 Pages) STMicroelectronics – Multistandard TV Audio Processor and Digital Sound Demodulator

STV82x6
Register List
Bit Name
HPD_IN
HPD_ON
SW_ON
Bits[4:3]
MUTE_LS
MUTE_SW
MUTE_HP
Reset
Function
0 Headphone Input Pin Status
Read only I²C bit that displays the HPD pin Status
0: Headphone is detected
1: Headphone is not detected
0 Headphone Detection Enable
0: Headphone Detection is disabled
1: Headphone Detection is enabled. If the HPD_IN bit is set, the Loudspeaker and Subwoofer
mute is activated
0 Subwoofer Enable
Before switching on/off the subwoofer, a mute is recommended to prevent an audible plop.
0: Subwoofer is disabled. Headphone output is selected.
1: Subwoofer is enabled. Subwoofer output is selected and Headphone output is in Mono mode
00 Reserved.
000 _{000: LS + SW + HP mono}
001: LS + SW
010: LS + HP stereo
011: LS only
100: Not used.
101: Not used.
110: HP stereo only.
111: All muted (Default)
9.4 Clocking
Note:
A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described
below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the
frequency recommended for reducing potential RF interference in the application. (See Section
2.2: System Clock.) However, if necessary, the PLL Clock can be re-programmed for other quartz
crystal frequencies within a range from 23 to 30 MHz. Other quartz crystal frequencies can be
programmed on your demand.
A Crystal Frequency change is compatible with other default I²C programming including the built-in
Automatic Standard Recognition System.
PLL_DIV
Address (hex): 08h
Type: R/W
Bit 7
Bit 6
0
0
PLL Frequency Divider Register
Bit 5
Bit 4
SDIV[2:0]
Bit 3
Bit 2
Bit 1
FDIV[2:0]
Bit 0
Bit Name
Bits[7:6]
SDIV[2:0]
FDIV[2:0
Reset
00 Reserved.
000 PLL Frequency S-Divider
101 PLL Frequency F-Divider
Function
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