AN3995 Datasheet, PDF (39/49 Pages) STMicroelectronics – Getting started tutorial

AN3995
Application code example
__ghs_board_memory_init:
#/**************************************************************************/
#/* MMU configuration code for SRAM
*/
#/* TLB1, Entry 1 128KB 0x4000_0000 to 0x4001_FFFF */
#/**************************************************************************/
e_lis r3, 0x1001
mtmas0 r3
#/* MAS0 */
e_lis r3, 0xC000
e_or2i r3, 0x0380
mtmas1 r3
#/* MAS1 = 0xC0000380 (128Kb) */
e_lis r3, 0x4000
e_or2i r3, 0x0028
mtmas2 r3
#/* MAS2 = 0x40000028 */
e_lis r3, 0x4000
e_or2i r3, 0x003F
mtmas3 r3
#/* MAS3 = 0x4000003F */
tlbwe
#/* Write the entry to the TLB */
#/**************************************************************************/
#/* MMU configuration code for Peripheral Area (IPBridge)
*/
#/* TLB1, entry 2 1GB 0xC000_0000 to 0xFFFF_FFFF
*/
#/**************************************************************************/
e_lis r3, 0x1002 #/* MAS0, Configure TLB1, Entry 2 */
mtmas0 r3
e_lis r3, 0xC000 #/* MAS1 = 0xC0000A00 */
e_or2i r3, 0x0A00
mtmas1 r3
e_lis r3, 0xC000 #/* MAS2 = 0xC000002A */
e_or2i r3, 0x002A
mtmas2 r3
e_lis r3, 0xC000 #/* MAS3 = 0xC000003F */
e_or2i r3, 0x003F
mtmas3 r3
tlbwe
#/* Write the entry to the TLB */
#/**************************************************************************/
#/* Initialize all SRAM space by copying all 32GPR's to RAM (fast) */
#/* Counter defines number of 32 x 32-bit words needed to write to RAM */
#/**************************************************************************/
e_lis r5, _SRAM_ADDR_Z4@h #/* SRAM start address defined in the linker file */
e_or2i r5, _SRAM_ADDR_Z4@l
e_lis r6, _SRAM_SIZE_Z4@h
e_or2i r6, _SRAM_SIZE_Z4@l
#/* SRAM size defined in the linker file */
e_srwi r6, r6, 0x7
mtctr r6
#/* Divide SRAM size by 128 bytes */
#/* Move to counter for use with "bdnz" */
sram_loop:
e_stmw r0,0x0(r5)
e_addi r5,r5,128
e_bdnz sram_loop
#/* Write all 32 registers to SRAM */
#/* Increment the RAM pointer to next */
#/* 128byte(4bytes*32 registers) */
#/* Loop for all of SRAM */
#/**************************************************************************/
#/* Flash Wait States and MMU configurations code will be copied to SRAM*/
#/* to avoid inconsistencies
*/
Doc ID 022384 Rev 2
39/49