L6701 Datasheet, PDF (38/44 Pages) STMicroelectronics – 3 Phase Controller for VR10, VR9 and K8 CPUs

16 Layout Guidelines
16 Layout Guidelines
L6701
Since the device manages control functions and high-current drivers, layout is one of the most
important things to consider when designing such high current applications. A good layout
solution can generate a benefit in lowering power-dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the
performance of the control loops.
Two kind of critical components and connections have to be considered when layouting a VRM
based on L6701: power components and connections and small signal components
connections.
16.1 Power Components and Connections
These are the components and connections where switching and high continuous current flows
from the input to the load. The first priority when placing components has to be reserved to this
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a
power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, i.e. the power transistors, must be close one to the other.
The use of multi-layer printed circuit board is recommended.
Figure 20 shows the details of the power connections involved and the current loops. The input
capacitance (C_IN), or at least a portion of the total capacitance needed, has to be placed close
to the power section in order to eliminate the stray inductance generated by the copper traces.
Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS
drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance
and resistance associated to the copper trace also adding extra decoupling capacitors along
the way to the load when this results in being far from the bulk capacitor bank.
Gate traces must be sized according to the driver RMS current delivered to the power
MOSFET. The device robustness allows managing applications with the power section far from
the controller without losing performances. Anyway, when possible, it is suggested to minimize
the distance between controller and power section.
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