STM32F107VBT6 Datasheet, PDF (36/103 Pages) STMicroelectronics – Connectivity line, ARM-based 32-bit MCU

Electrical characteristics
STM32F105xx, STM32F107xx
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for T_A.
Table 10. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
V_DD rise time rate
0
t_VDD
V_DD fall time rate
20
Max
Unit
∞
µs/V
∞
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient
temperature and V_DD supply voltage conditions summarized in Table 9.
Table 11. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge)
2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
V_PVD
Programmable voltage ^{PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V}
detector level selection _{PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V}
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3
V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
V_PVDhyst(2) PVD hysteresis
100
mV
V_POR/PDR
Power on/power down
reset threshold
Falling edge
Rising edge
1.8^{(1) 1.88 1.96 V}
1.84 1.92 2.0 V
V_PDRhyst(2) PDR hysteresis
T_RSTTEMPO(2) Reset temporization
40
mV
1 2.5 4.5 ms
1. The product behavior is guaranteed by design down to the minimum V_POR/PDR value.
2. Guaranteed by design, not tested in production.
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Doc ID 15274 Rev 6