L6566B_08 Datasheet, PDF (36/51 Pages) STMicroelectronics – Multi-mode controller for SMPS

Application information
Figure 23. OVP function: timing diagram
L6566B
GD
(pin 4)
Vaux
t
0
ZCD
(pin 11)
t
5V
COUT
t
STROBE
2 µs
0.5 µs
t
t
OVP
COUNTER
RESET
COUNTER
STATUS
0
0
FAULT
t
t
0
0 →1
1 →2
2 →0
0
0 →1
1 →2
2 →3
3 →4
t
NORMAL OPERATION
TEMPORARY DISTURBANCE
t
FEEDBACK LOOP FAILURE
Note:
The value of R_Z1 will be such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 14
R _Z1
≥
1
3 ⋅ 10 ^−3
Naux
Np
Vin_max
where Vin_max is the maximum dc input voltage and Ns the turn number of the primary
winding. See Section 5.2: Zero current detection and triggering block; oscillator block on
page 21 for additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, first
the OVP comparator is active only for a small time window (typically, 0.5 µs) starting 2 µs
after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges
of the voltage across the auxiliary winding Vaux; second, to stop the L6566B the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided to
this purpose.
Figure 22 on page 35 shows the internal block diagram, while the timing diagrams in
Figure 23 illustrate the operation.
To use the OVP function effectively, i.e. to ensure that the OVP comparator will be always
interrogated during MOSFET’s OFF-time, the duty cycle D under open-loop conditions must
fulfill the following inequality:
36/51