STM32F103VDT6 Datasheet, PDF(35/130 Page) STMicroelectronics – High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

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STM32F103VDT6 Datasheet, PDF (35/130 Pages) STMicroelectronics – High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

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STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Table 5.

High-density STM32F103xx pin definitions (continued)

Pins

Alternate functions(4)

Pin name

Main

function(3)

(after reset)

Default

Remap

PB3/TRACESWO

A7 A7 A4 55 89 133

PB3

I/O FT JTDO

SPI3_SCK / I2S3_CK/

TIM2_CH2 /

SPI1_SCK

A6 A6 B4 56 90 134

PB4

I/O FT NJTRST

SPI3_MISO

PB4 / TIM3_CH1

SPI1_MISO

B6 C5 A5 57 91 135

PB5

C6 B5 B5 58 92 136

PB6

D6 A5 C5 59 93 137

PB7

I/O

PB5

I2C1_SMBA/ SPI3_MOSI

I2S3_SD

TIM3_CH2 /

SPI1_MOSI

I/O FT

PB6

I2C1_SCL(8)/ TIM4_CH1(8) USART1_TX

I/O FT

PB7

I2C1_SDA(8) /

FSMC_NADV /

TIM4_CH2(8)

USART1_RX

D5 D5 A6 60 94 138 BOOT0

I

BOOT0

C5 B4 D5 61 95 139

PB8

I/O FT

PB8

TIM4_CH3(8)/SDIO_D4

I2C1_SCL/

CAN_RX

B5 A4 B6 62 96 140

PB9

I/O FT

PB9

TIM4_CH4(8)/SDIO_D5

I2C1_SDA /

CAN_TX

A5 D4 - - 97 141

PE0

I/O FT

PE0

TIM4_ETR / FSMC_NBL0

A4 C4 - - 98 142

PE1

I/O FT

PE1

FSMC_NBL1

E5 E5 A7 63 99 143

VSS_3

S

VSS_3

F5 F5 A8 64 100 144

VDD_3

S

VDD_3

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3

mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load

of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead.

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,

available from the STMicroelectronics website: www.st.com.

9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the

functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and

LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,

refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

10. For devices delivered in LQFP64 packages, the FSMC function is not available.

Doc ID 14611 Rev 8

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