ST7LITE1XB_08 Datasheet, PDF(35/159 Page) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

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ST7LITE1XB_08 Datasheet, PDF (35/159 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

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ST7LITE1xB

SYSTEM INTEGRITY MANAGEMENT (Contâd)

7.6.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read / Write

Reset Value: 0110 0xx0 (6xh)

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

LOCK

CR1

CR0

WDG

LOCKED LVDRF AVDF AVDIE

Bit 7 = LOCK32 PLL 32Mhz Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL 32Mhz reaches its oper-

ating frequency

0: PLL32 not locked

1: PLL32 locked

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

adjust the RC oscillator frequency and to obtain an

accuracy of 1%. Refer to section 7.3 on page 25.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(reading the SICSR register or writing 0 to this bit)

or by an LVD Reset (to ensure a stable cleared

state of the WDGRF flag when the CPU starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

RESET Sources

LVDRF WDGRF

External RESET pin

Watchdog

LVD

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (by reading). When

Bit 1 = AVDF Voltage Detector Flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit is set. Refer to Figure

20 and to Section 7.6.2.1 for additional details.

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 = AVDIE Voltage Detector Interrupt Enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag is

set. The pending interrupt information is automati-

cally cleared when software enters the AVD inter-

rupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

PLL TEST REGISTER (PLLTST)

Read / Write

Reset Value: 0000 0000 (00h)

PLLdiv2 0 0

Bit 7 : PLLdiv2 PLL clock divide by 2

This bit is read or write by software and cleared by

hardware after reset. This bit will divide the PLL

output clock by 2.

0 : PLL output clock

1 : Divide by 2 of PLL output clock

Refer âClock Management Block Diagramâ on

page 26

Note : Write of this bit will be effective after 2 Tcpu

cycles (if system clock is 8mhz) else 1 cycle (if

system clock is 4mhz) i.e. effective time is 250ns.

Bit 6:0 : Reserved , Must always be cleared

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