L6566BH Datasheet, PDF (35/51 Pages) STMicroelectronics – Multimode controller for SMPS

L6566BH
Figure 23. OVP function: timing diagram
Application information
Note:
GD
(pin 4)
Vaux
t
0
ZCD
(pin 11)
t
5V
COUT
t
STROBE
2 µs
0.5 µs
t
t
OVP
COUNTER
RESET
COUNTER
STATUS
0
0
FAULT
t
t
0
01
12
20
0
01
12
23
34
t
NORMAL OPERATION
TEMPORARY DISTURBANCE
t
FEEDBACK LOOP FAILURE
AM11499v1
The value of R_Z1 is such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 14
R _Z1
≥
1
3 ⋅ 10 ^−3
Naux
Np
Vin_max
where Vin_max is the maximum DC input voltage and Ns the turn number of the primary
winding. See Section 5.2: Zero-current detection and triggering block; oscillator block for
additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, firstly
the OVP comparator is active only for a small time frame (typically, 0.5 µs) starting 2 µs after
MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of the
voltage across the auxiliary winding Vaux; secondly, to stop the L6566BH, the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided for
this purpose.
Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23 illustrate
the operation.
To use the OVP function effectively, i.e. to ensure that the OVP comparator is always
interrogated during MOSFET OFF-time, the duty cycle D under open loop conditions must
fulfill the following inequality:
Doc ID 16610 Rev 2
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