ST72101_01 Datasheet, PDF (34/85 Pages) STMicroelectronics – 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS

ST72101/ST72212/ST72213
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register).
two steps:
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t _{LS Byte}
Returns the buffered
LS Byte value at t0
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
Sequence completed
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
) _{This buffered value remains unchanged until the}
t(s ^{16-bit read sequence is completed, even if the}
c ^{user reads the MS Byte several times.}
u _{After a complete reading sequence, if only the}
d _{CLR register or ACLR register are read, they re-}
ro turn the LS Byte of the count value at the time of
P ^{the read.}
te ^{Whatever the timer mode used (input capture, out-}
put compare, One Pulse mode or PWM mode) an
le _{overflow occurs when the counter rolls over from}
o _{FFFFh to 0000h then:}
bs ^{– The TOF bit of the SR register is set.}
O – A timer interrupt is generated if:
- _{– TOIE bit of the CR1 register is set and}
t(s) ^{– I bit of the CC register is cleared.}
If one of these conditions is false, the interrupt re-
c _{mains pending to be issued as soon as they are}
Obsolete ^{Produ both true.}
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
5.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
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