AN4570 Datasheet, PDF (34/46 Pages) STMicroelectronics – This application note describes how to use the high-density

Interfacing with an 8-bit NAND Flash memory
AN4570
Based on the NAND Flash memory access timings shown in Figure 10, the following
equations are found:
• The write or read access time is the time between the falling edge and the rising edge
of the NAND Flash memory Chip Select signal. It is computed as a function of the FMC
timing parameter:
((SET + 1) + (WAIT + 1) + (HOLD + 1)) × t_HCLK ≥ Write/Read access
• The Wait time is measured between the falling edge and the rising edge of the
Write/Read Enable signal:
Write/Read Enable signal low to high = (WAIT + 1) × t_HCLK
• For write access, the HIZ parameter is the time measured between the falling edge of
the Chip Select signal and the data setup on bus:
(HIZ+1) x t_HCLK ≥ Chip Select setup time to Data setup.
• The HOLD timing is given in the NAND datasheet as follows:
(HOLD +1) x t_HCLK = Write Enable High to Chip Enable / Address/Command Latch
High
To make sure of the correct timing configuration of the FMC, the timings have to take into
consideration:
• The maximum read/write access time
• The different internal FMC delays
• The different internal memory delays
Note:
Hence, we have the following equations following the NAND512W3A NAND datasheet:
• (SET + 1) x t_HCLK ≥ max (t_CS, t_CLS, t_ALS, t_CLR, t_AR) - t_WP
• (WAIT + 1) x t_HCLK ≥ max (tWP, tRP)
• (HIZ + 1) x t_HCLK ≥ max (t_CS, t_ALS, t_CLS) + (t_WP - t_DS)
• (HOLD + 1) x t_HCLK ≥ max (t_CH, t_CLH, t_ALH)
• ((WAIT + 1) + (HOLD + 1) + (SET + 1)) x t_HCLK ≥ max (t_WC/RC)
Considering the different timings in the FMC and the memory, the equations become:
• WAIT must verify:
(WAIT + 1)× t_HCLK ≥ (t_REA + t_su(D-NOE))
WAIT ≥ (t_REA + t_su(D-NOE)) /t_HCLK - 1
t_su(D-NOE) is specified in the STM32F30xxD/E datasheets.
t_su(D-NOE) = 25 ns
Table 8 gives the meanings and values of the NAND512W3A2C memory parameters.
Table 8. NAND512W3A2C Flash memory timings
Symbol
Parameter
Value
Unit
t_CEA
Chip Enable low to output valid
t_WP
Write Enable low to Write Enable high
35
ns
15
ns
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