STV0684 Datasheet, PDF (33/49 Pages) STMicroelectronics – Digital Camera Processor

STV0684
Electrical Characteristics
Table 11: SPI timing table
Symbol
Parameter
t_CSS
SS active Setup time, relative to SCK
t_CHSH
SS active hold time, relative to SCK
t_V
Clock low to output valid
Min
210(master/
slave)
50(master/
slave)
t_CS
Minimum SS high time
120(slave)
t_idle
Idle phase between byte transfer in transmit mode for 120(slave)
resynchronisation
Max
Units
ns
ns
20
ns
(master/slave)
ns
ns
In slave mode for resynchronization purpose the need for idle phase between byte transfer is
needed for the transmit mode.
Figure 11: Idle phase timing in slave mode
t_idle
sck
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