ST25RU3993 Datasheet, PDF (33/90 Pages) STMicroelectronics – Integrated supply regulators

ST25RU3993
Functional overview
2.8.2
already sent to the FIFO, the host system waits until the last data byte has been sent. The
end of the transmission is signaled to the MCU by the IRQ request irq_TX in register 37h.
The two Tx length register 1 and Tx length register 2 (3Dh, 3Eh) support incomplete byte
transmission. The MCU needs to define the number of complete bytes and the number of
the remaining bits that should be transmitted.
TX direct mode
Direct mode is chosen when using only analog functions, bypassing all the protocol
handling support of the reader device.
Entering and terminating the Direct Mode
To enter the direct mode the direct command Direct Mode (81h) should be sent followed by
a NCS low-to-high transition. The direct mode remains active as long as NCS is kept high.
To terminate the direct mode the direct command Block Rx (96h) needs to be sent
immediately after the NCS high-to-low transition. During the same or consecutive NCS low
periods normal communication via the SPI interface is possible again.
Direct Mode Signals
The Table 6 shows the re-assignments of the I/O pins during the direct mode. The different
reception outputs options are related to the dir_mode option bit in the Protocol selection
register (01h).
Pin Name
MOSI
SCLK
MISO
IRQ
Table 6. I/O pin reassignment in direct mode
Bit Stream and Bit Clock Output
(dir_mode = 0)
Sub Carrier Output
(dir_mode = 1)
Tx data input
Enable Rx input
Rx data output
Rx bit clock output
Tx data input
Enable Rx input
I-Channel subcarrier output
Q-Channel subcarrier output
In the direct mode the MCU must directly control the transmission modulation input pin
MOSI (Tx data input). The RF field is set to a high level if MOSI is high and to low if MOSI is
low. The circuitry shapes the field according to the settings in the Modulator control register
1 and Modulator control register 3 (13h-15h) and transmits the signal.
2.9
Receiver
The receiver section comprises two input mixers followed by a fast AC coupling, gain and
filtering stages, and a digitizer. The two received signals are fed to the decision circuitry, the
bit-decoder and the framer, where the preamble is removed and CRC is checked. The
clean, framed baseband data is accessible for the MCU via the 24-byte FIFO I/O register
(3Fh).
The receiver section is activated by the option bits rec_on or rf_on from the Device status
control register (00h). The typical bias settling time is 3 ms if the reader device was
previously in the normal mode (EN=H and stby=0). If the rec_on bit is set together with the
EN pin or a stby high-low change, the normal mode power-up timing prevails.
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