L6566A_08 Datasheet, PDF (33/51 Pages) STMicroelectronics – Multi-mode controller for SMPS with PFC front-end

L6566A
Application information
Figure 20. Operation after latched disable activation: timing diagram
DIS
(pin 8)
4.5V
Vcc
(pin 5)
VccON
VccON -0.5
VccOFF
HV generator is turned on
Vccrestart
GD
(pin 4)
Restart is quicker
t
Disable latch is reset here
t
HV generator turn-on is disabled here
Vcc_PFC
t
(pin 6)
Vin
Input source is removed here
t
VHVstart
AC_OK
t
(pin 16)
Vth
t
5.10
Soft-start and delayed latched shutdown upon overcurrent
At device start-up, a capacitor (Css) connected between the SS pin (14) and ground is
charged by an internal current generator, I_SS1, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin 15, (see “Section 5.6: PWM comparator, PWM
latch and voltage feedforward blocks on page 27”); MOSFET’s conduction time increases
gradually, hence controlling the start-up inrush current. The time needed for the overcurrent
setpoint to reach its steady state value, referred to as soft-start time, is approximately:
Equation 9
T_SS
=
Css
I_SS1
V_csx (V_VFF )
=
Css
I_SS1
⎜⎜⎝⎛¹
−
V_VFF
3
⎟⎟⎠⎞
During the ramp (i.e. until V_SS = 2 V) all the functions that monitor the voltage on pin COMP
are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at start-up, but may be also caused by either a control loop failure or a converter
overload/short circuit. A control loop failure results in an output overvoltage that is handled
by the OVP function of the L6566A (see next section). In case of QR operation, a short
circuit causes the converter to run at a very low frequency, then with very low power
capability. This makes the self-supply system that powers the device unable to keep it
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