ST7232A Datasheet, PDF (31/154 Pages) STMicroelectronics – 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE

ST7232A
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Exit
from
ACTIVE
HALT
Address
Vector
RESET
TRAP
Reset
Software interrupt
yes
N/A
no
0
Not used
1
MCC/RTC
Main clock controller time base inter-
rupt
MCCSR
Higher
yes
Priority
2
ei0
External interrupt port A3..0
yes
3
ei1
External interrupt port F2..0
yes
N/A
4
ei2
External interrupt port B3..0
yes
5
ei3
External interrupt port B7..4
yes
6
Not used
7
SPI
SPI peripheral interrupts
SPICSR
yes ¹⁾
8 TIMER A TIMER A peripheral interrupts
TASR
no
9 TIMER B TIMER B peripheral interrupts
TBSR
no
10
SCI
SCI Peripheral interrupts
11
Not used
SCISR _Lower no
Priority
Note 1: Unexpected exit from HALT may occur when SPI is in slave mode.
yes FFFEh-FFFFh
no FFFCh-FFFDh
FFFAh-FFFBh
yes FFF8h-FFF9h
no FFF6h-FFF7h
no FFF4h-FFF5h
no FFF2h-FFF3h
no FFF0h-FFF1h
FFEEh-FFEFh
no FFECh-FFEDh
no FFEAh-FFEBh
no FFE8h-FFE9h
no FFE6h-FFE7h
FFE4h-FFE5h
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 18). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
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