STA333IS Datasheet, PDF (30/43 Pages) STMicroelectronics – 100 dB SNR and dynamic range

Register description
STA333IS
5.2
5.2.1
Volume control registers (addr 0x06 to 0x09)
Mute/line output configuration register (addr 0x06)
D7
D6
D5
D4
Reserved
0
0
0
0
Master mute
D3
D2
D1
C2M
C1M
0
0
0
Bit
0
R/W
R/W
RST
0
Table 39. Master mute
Name
Description
MMUTE
0: normal operation
1: all channels are in mute condition
D0
MMUTE
0
Channel mute
Bit
1
2
R/W
R/W
R/W
RST
0
0
Table 40. Channel mute
Name
Description
C1M
C2M
Channel 1 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
Channel 2 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
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