M25PE40 Datasheet, PDF (30/60 Pages) STMicroelectronics – 4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

Instructions
M25PE40
6.8
Note:
Read Lock Register (RDLR)
The Read Lock Register (RDLR) instruction is decoded only in the in the T9HX process
(see Important note on page 6).
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector (or subsector). Each address bit is latched-in during
the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on
Serial Data Output (Q), each bit being shifted out, at a maximum frequency f_C, during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9. Lock Registers
Bit
Bit Name Value
Function
b7-b4
Reserved
The Write Lock and Lock Down Bits cannot be changed. Once a
‘1’ ‘1’ is written to the Lock Down Bit it cannot be cleared to ‘0’,
b1
Sector Lock
Down
except by a Reset or power-up.
‘0’
The Write Lock and Lock Down Bits can be changed by writing
new values to them. (Default value).
b0
Sector Write
Lock
‘1’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’
Write, Program and Erase operations in this sector are executed
and will modify the sector contents. (Default value).
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
D
23 22 21 3 2 1 0
MSB
High Impedance
Q
Lock Register Out
76543 210
MSB
AI10783
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