M24128-A125 Datasheet, PDF (30/40 Pages) STMicroelectronics – Automotive 128-Kbit serial IC bus EEPROM with 1 MHz clock

DC and AC parameters
M24128-A125
Symbol Alt.
Table 12. 1 MHz AC characteristics
Parameter⁽¹⁾
Min.
Max.
Unit
f_C
f_SCL Clock frequency
0
t_CHCL
t_HIGH Clock pulse width high
260
t_CLCH
t_LOW Clock pulse width low
400
t_XH1XH2
t_R Input signal rise time
(2)
t_XL1XL2
t_F Input signal fall time
(2)
t_QL1QL2(3)
t_F SDA (out) fall time
-
t_DXCX
t_SU:DAT Data in setup time
50
t_CLDX
t_HD:DAT Data in hold time
0
t_CLQX(4)
t_DH Data out hold time
100
t_CLQV(5)
t_AA Clock low to next data valid (access time)
-
t_CHDL
t_SU:STA Start condition setup time
250
t_DLCL
t_HD:STA Start condition hold time
250
t_CHDH t_SU:STO Stop condition setup time
250
t_DHDL
t_BUF
Time between Stop condition and next Start
condition
500
t_WLDL(6) ⁽³⁾ t_SU:WC WC set up time (before the Start condition)
0
t_{DH(W3)H(7) tHD:WC WC hold time (after the Stop condition)}
1
1
MHz
-
ns
-
ns
(2)
ns
(2)
ns
120
ns
-
ns
-
ns
-
ns
450
ns
-
ns
-
ns
-
ns
-
ns
-
µs
-
µs
t_W
t_WR Write time
-
t_NS(3)
-
Pulse width ignored (input filter on SCL and
SDA)
-
4
ms
80
ns
1. Test conditions (in addition to those in Table 7 and Table 8).
2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
f_C < 1 MHz.
3. Characterized only, not tested in production.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5.
t0_C.7LQVVCi_Cs,thaesstuimmein(gfrothmatththeefaRllbinugs
edge of
× Cbus
SCL) required by the SDA
time constant is within the
vbauluselisnesptoecriefiaecdhineiF^thig^eu^r r⁰e^.311^V.CC
or
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
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