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TSM103AIDT Datasheet, PDF (3/9 Pages) STMicroelectronics – DUAL OPERATIONAL AMPLIFIER AND VOLTAGE REFERENCE
TSM103/A
OPERATOR 2 (independent op-amp)
VCC+ = +5V, VCC = Ground, Vo = 1.4V,Tamb = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vio
Input Offset Voltage
TSM103, Tamb = 25°C
Tmin. ≤ Tamb ≤ Tmax.
TSM103A, Tamb = 25°C
Tmin. ≤ Tamb ≤ Tmax.
mV
1
4
5
0.5
2
3
DVio
Input Offset Voltage Drift
7
µV/°C
Iio
Input Offset Current
Tmin. ≤ Tamb ≤ Tmax.
2
30
nA
50
Iib
t(s) Avd
uc SVR
rod Vicm
lete P CMR
so Isource
Ob Io
t(s) - Isink
uc VOH
te Prod VOL
Obsole SR
Input Bias Current
Tmin. ≤ Tamb ≤ Tmax
Large Signal Voltage Gain
VCC = 15V, RL = 2k, Vo = 1.4V to 11.4V
Tmin. ≤ Tamb ≤ Tmax.
Supply Voltage Rejection Ratio
VCC = 5V to 30V
Input Common Mode Voltage Range
VCC = +30V - see note 1)
Tmin. ≤ Tamb ≤ Tmax.
Common Mode Rejection Ratio
Tmin. ≤ Tamb ≤ Tmax.
Output Current Source
VCC = +15V, Vo = 2V, Vid = +1V
Short Circuit to Ground
VCC = +15V
Output Current Sink
Vid = -1V,
VCC = +15V, Vo = 2V
High Level Output Voltage
VCC+ = 30V
Tamb = 25°C, RL = 10k
Tmin. ≤ Tamb ≤ Tmax.
Low Level Output Voltage
RL = 10k
Tmin. ≤ Tamb ≤ Tmax.
Slew Rate at Unity Gain
Vi = 0.5 to 3V, VCC = 15V
RL = 2k, CL = 100pF, unity gain
20
150
nA
200
50
100
25
V/mV
dB
65
100
V
0
(VCC+) -1.5
0
(VCC+) -2
70
85
dB
60
mA
20
40
mA
40
60
mA
10
20
V
27
28
27
5
0.2
0.4
mV
20
20
V/µs
GBP Gain Bandwidth Product
MHz
VCC = 30V,RL = 2k, CL = 100pF
f = 100kHz, Vin = 10mV
0.5
0.9
THD Total Harmonic Distortion
%
f = 1kHz
0.02
AV = 20dB,RL = 2k, VCC = 30V
CL = 100pF, Vo = 2Vpp
1. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of
the common-mode voltage range is VCC+ - 1.5V.
But either of both inputs can go to +36V without damage.
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