STB7NA40 Datasheet, PDF (3/10 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

STB7NA40
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Sy mbo l
td(on)
t_r
(di/ dt)_on
Q_g
Q_gs
Q_gd
P ar am et e r
Turn-on Time
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
T est Con ditio ns
VDD = 200 V ID = 3.5 A
R_G = 47 Ω
V_GS = 10 V
(see test circuit, figure 3)
V_DD = 320 V I_D = 7 A
RG = 47 Ω
VGS = 10 V
(see test circuit, figure 5)
V_DD = 320 V I_D = 7 A V_GS = 10 V
Min.
T yp.
25
75
220
34
7
15
Max.
35
100
45
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Sy mbo l
t_{r( Vo ff )}
t_f
tc
P ar am et e r
Off-voltage Rise Time
Fall Time
Cross-over Time
T est Con ditio ns
V_DD = 320 V I_D = 7 A
R_G = 47 Ω V_GS = 10 V
(see test circuit, figure 5)
Min.
T yp.
40
25
75
Max.
55
35
100
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Sy mbo l
P ar am et e r
T est Con ditio ns
ISD
ISDM (• )
V_SD (∗)
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
I_SD = 6.5 A V_GS = 0
trr
Reverse Recovery
Time
Qrr
Reverse Recovery
ISD = 7 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 ^oC
(see test circuit, figure 5)
Char ge
IRRM Reverse Recovery
Cur ren t
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limi ted by safe operating area
Min.
T yp.
Max.
6 .5
26
Unit
A
A
1 .6
V
380
ns
4.8
µC
25
A
Safe Operating Area
Thermal Impedance
3/10