M5480 Datasheet, PDF (3/6 Pages) STMicroelectronics – LED DISPLAY DRIVER

M5480
STATIC ELECTRICAL CHARACTERISTICS
(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V,unless otherwise specified)
Symbol
VDD
IDD
VI
Parameter
Supply Voltage
Supply Current
Input Voltages Logical "0" Level
Logical "1" Level
IB
VB
VO(off)
IO
Brightness Input Current (note 2)
Brightness Input Voltage (pin 13)
Off State Output Voltage
Output Sink Current (note 3)
Segment OFF
Segment ON
fclock Input Clock Frequency
IO Output Matching (note 1)
Test Conditions
VDD = 13.2 V
± 10 µA Input Bias
4.75 ≤ VDD ≤ 5.25
VDD > 5.25
Input Current = 750µA, Tamb = 25^oC
VO = 3 V
VO = 1 V (note 4)
Brightness In. = 0 µA
Brightness In. = 100 µA
Brightness In. = 750 µA
Min.
4.75
Typ.
– 0.3
2.2
VDD – 2
0
3
13.2
0
2
2.7
12
15
0
Max.
13.2
7
0.8
VDD
VDD
0.75
4.3
18
10
10
4
25
0.5
± 20
Notes : 1. Output matching is calculated as the percent variation from IMAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
3. Absolute maximum for each output should be limited to 40 mA.
4. The VO voltage should be regulated by the user
Unit
V
mA
V
V
V
mA
V
V
µA
µA
mA
mA
MHz
%
FUNCTIONAL DESCRIPTION
The M5480 is specifically designed to operate 3 1/2
digit alphanumeric displays with minimal interface
with the display and the data source. Serial data
transfer from the data source to the display driver
is accomplished with 2 signals, serial data and
clock. Using a format of a leading "1" followed by
the 35 data bits allows data transfer without an
additional load signal. The 35 data bits are latched
after the 36th bit is complete, thus providing non-
multiplexed, direct drive to the display.
Outputs change only if the serial data bits differ
from the previous time.
Display brightness is determined by control of the
output current for LED displays. A 1nF capacitor
should be connected to brightness control, pin 13,
to prevent possible oscillations.
Figure 2 : Input Data Format
A block diagram is shown in Figure 1. The output
current is typically 20 times greater than the current
into pin 13, which is set by an external variable
resistor.
There is an internal limiting resistor of 400 Ω nomi-
nal value.
Figure 2 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
At the low state of the clock a RESET signal is
generated which clears all the shift registers for the
next set of data. The shift registers are static mas-
ter-slave configurations. There is no clear for the
master portion of the first register, thus allowing
continuous operation.
1
36
CLOCK
DATA
START BIT 1
BIT 34 BIT 35
LOAD
(INTERNAL)
RESET
(INTERNAL)
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