M48T35 Datasheet, PDF (3/18 Pages) STMicroelectronics – 256 Kbit 32Kb x8 TIMEKEEPER SRAM

Table 3. Operating Modes ⁽¹⁾
Mode
V_CC
E
G
Deselect
V_IH
X
Write
Read
4.75V to 5.5V
or
4.5V to 5.5V
V_IL
X
V_IL
V_IL
Read
V_IL
V_IH
Deselect
V_SO to V_PFD (min) ⁽²⁾
X
X
Deselect
≤ V_SO
X
X
Note: 1. X = V_IH or V_IL; V_SO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Figure 3. Block Diagram
M48T35, M48T35Y
W
DQ0-DQ7
Power
X
High Z
Standby
V_IL
D_IN
V_IH
D_OUT
V_IH
High Z
Active
Active
Active
X
High Z
CMOS Standby
X
High Z Battery Back-up Mode
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
32,760 x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
VCC
VSS
AI01623
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28-
BR12SH1".
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35/35Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad-
dresses 7FF8h-7FFFh.
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