HCC4099B Datasheet, PDF (3/14 Pages) STMicroelectronics – 8-BIT ADDRESSABLE LATCH

LOGIC DIAGRAM
1 of 8 latches
HCC/HCF4099B
Definition of WRITE DIABLE ON Time
Master Timing Diagram
Mode Selection
Types _{W D R}
Addressed
Latch
Unaddressed
Latch
A 0 0 Follows Data Holds Previous
State
B 0 1 Follows Data
Reset to ”0”
(active high 8-channel
demultiplexer)
C 10
Holds Previous State
D 1 1 Reset to ”0”
Reset to ”0”
WD = WRITE DISABLE
R = RESET
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