ESM1602B Datasheet, PDF (3/11 Pages) STMicroelectronics – QUAD COMPARATOR INTERFACE CIRCUIT

ESM1602B
ELECTRICAL CHARACTERISTICS
VCC = +35V, -25^oC ≤ Tamb ≤ +85^oC (unless otherwise specified)
Symbol
VI
V_I
+
–
V_C
I_IB
I_SC
V_CC–V_O
V_O
I_CC
S_VO
V_F
–
–
Parameter
Input Voltage Range - Note 1
Non-inverting Input
Inverting Input
Input Control Voltage (2V < V_CM < 33V) - Note 2
Input Bias Current - Note 3
Short-circuit Output Current
V_CC = +10 to +35 V
Output Saturation Voltage (high level) - (I_O = –10mA)
Output Saturation Voltage (high level) - (I_O = –10mA)
Supply Current
R_L = ∞ for the 4 Comparators
R_L Common for the 4 Comparators
Output Slew-rate (R_L = 3kΩ, T_amb = +25^oC)
Input Protective Diode Forward Voltage
(I = 20mA, T_amb = +25^oC)
Energy of Pulses against which Circuit Output is Protected
(Tamb = +25^oC) - Note 4
Pulsed Current Applied to Protective Output Diodes
(T_amb = +25^oC) - Note 5
Min.
0
2
150
6
1
Typ.
1
1
1
4
10
0.4
Max.
33
33
500
5
25
1.5
1.6
6
13
1.5
20
Typ. Fig.
V
V
mV
µA
mA
V
V
mA
mA
V/µs
V
8
9
11
12
13,14
mJ
A
15
No tes : 1. When negative input is biased between 0 and 2 volts output is always low.
2. Comparator hysteresis voltage on positive input on the one hand and negative input on the other hand equals sum of input control
voltages VC1 + VC2 or VC3 + VC4.
3. Input current flows out of the circuit owing to PNP input stage. This current is constant and independent of output level. So no load
change is transmitted to inputs.
4. By definition, a circuit is immunized against powerful signals when no durable character istic change occurs after the application of
these signals and when the circuit has not been destroyed.
In industrial surroundings, parasitic signals contain usually high voltage (over 200 V) AC harmonics having variable impedance of
500 Ω to 10kΩ.
The powerdissipation of thesesignals is divided between clamping diodes and the VCC. Simulationis used to determine the maximum
energy level. The injected current value cannot in any case exceed 3A.
5. Output protective diodes are tested individually by means of positive and negative dischar ge voltages of a capacitor. The negative
discharge control occurs through a single diode. During positive discharge, due to the properties of integration, a grounded collector
PNP transistor appears in parallel with the clamping diode connected to VCC. A part of the current flows through this transistor, VCE
being greater than VCC. If T is the total discharge duration, energy dissipated in the circuit is :
T
W = _⌠⌡ [ i_{1 ⋅ vd +} i_{2 (VCC + vd)} ] _dt
O
For a certain injected current, the lower the current I2, that is to say the lower the PNP current gain the smaller the energy is dissipated in the cir-
cuit. Topology and technological processes have been chosen to shorten this current gain.
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