ESDAXXSC5 Datasheet, PDF (3/7 Pages) STMicroelectronics – QUAD TRANSIL ARRAY FOR ESD PROTECTION

CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage V_CL.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
ESDAxxSC5 / ESDAxxSC6
As the value of the dynamic resistance remains
stable for a surge duration lower than 20µs, the
2.5µs rectangular surge is well adapted. In
addition both rise and fall times are optimized to
avoid any parasitic phenomenon during the
measurement of Rd.
DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.
I
Ipp
2µs
t
tp = 2.5µs
2.5µs duration measurement wave.
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