ESDAVLC6-1BF4 Datasheet, PDF (3/9 Pages) STMicroelectronics – Multiple ESD strike sustainability

ESDAVLC6-1BF4
Characteristics
Figure 3. ESD response to IEC 61000-4-2
(typical values, +8 kV contact discharge)
10 V/div
1 71 V
2 41 V
1 VPP: ESD peak voltage
2 VCL :clamping voltage @ 30 ns
3 VCL :clamping voltage @ 60 ns
4 VCL :clamping voltage @ 100 ns
3 25 V
4 20 V
20 ns/div
Figure 4. ESD response to IEC 61000-4-2
(typical values, -8 kV contact discharge)
10 V/div
3 -24 V
2 -40 V
1 -72 V
4 -20 V
1 VPP: ESD peak voltage
2 VCL :clamping voltage @ 30 ns
3 VCL :clamping voltage @ 60 ns
4 VCL :clamping voltage @ 100 ns
20 ns/div
Figure 5. Junction capacitance versus reverse Figure 6. Relative variation of peak pulse power
applied voltage (typical values)
versus initial junction temperature
C (pF)
10
9
8
7
F=1 MHz
V_osc =30mV_RMS
T_j=25 °C
DIRECT /
REVERSE
P_PP(W)
100.0
80.0
8/20µs
Direct/Reverse
6
60.0
5
4
40.0
3
2
20.0
1
V_R(V)
0.0
T_j(°C)
0
25
35
45
55
65
75
85
95
0
1
2
3
4
5
6
Figure 7. Peak pulse power versus exponential
pulse duration
Figure 8. Leakage current versus junction
temperature (typical values)
P_PP(W)
1000.0
100.0
10.0
1.0
10
T_j = 25 °C
Direct/Reverse
IR (nA)
100.00
10.00
V_R = V_RM = 3 V
Direct/Reverse
1.00
0.10
t_P(µs)
0.01
Tj (°C)
100
1000
25
35
45
55
65
75
85
DocID023119 Rev 2
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