AN2593 Datasheet, PDF (3/15 Pages) STMicroelectronics – STR91x interrupt management

AN2593
STR91x vectored interrupt controller VIC
1
STR91x vectored interrupt controller VIC
1.1
VIC architecture overview
In the STR91x microcontroller, the Vectored Interrupt Controller VIC is implemented by
daisy-chaining two standard ARM primecells (PL190) VICs.
Figure 1 gives an overview of the hardware connections:
Figure 1. STR91x VIC architecture
VIC1.0
VIC1.15
VIC1
VIC0.0
VIC0.15
IRQ
VIC0
FIQ
ARM966
core
1.2
As shown in Figure 1, sixteen interrupt lines are connected to each VIC (see datasheet for
information about each interrupt source).
The choice of connecting two VICs in a daisy-chain was made in order to allow vectored
interrupt support for all 32 interrupt lines of the STR91x.
VIC operation
Figure 2 provides a schematic view of the VIC (single VIC) block diagram:
Figure 2. Overview of the VIC block diagram
FIQ
Interrupt source 0
Interrupt source 1
FIQ Logic
FIQ to CPU
Interrupt
Request
Logic
Interrupt source 15
IRQ
FIQ status Register
IRQ Priority
Logic
IRQ to CPU
Vectored Interrupt 0
Vectored Interrupt 0 ISR Address
Vector Address Register
Vectored Interrupt 15
Vectored Interrupt 15 ISR Address
IRQ status register
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