TDA7419_09 Datasheet, PDF (29/40 Pages) STMicroelectronics – 3 band car audio processor

TDA7419
5
I²C bus specification
I²C bus specification
5.1
5.1.1
5.1.2
5.1.3
Interface protocol
The interface protocol comprises:
● a start condition (S)
● a chip address byte (the LSB determines read/write transmission)
● a subaddress byte
● a sequence of data (N-bytes + acknowledge)
● a stop condition (P)
● the max. clock speed is 500 kbits/s
● 3.3 V logic compatible
Receive mode
S 1 0 0 0 1 0 0 R/W ACK TS AZ AI A4 A3 A2 A1 A0 ACK DATA ACK P
S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by μP)
"1" -> Transmission Mode (Data could be received by μP)
ACK = Acknowledge
P = Stop
TS = Testing mode
AZ = AutoZero remain
AI = Auto increment
Transmission mode
S 1 0 0 0 1 0 0 R/W ACK X X X X X X X SM ACK P
SM = Soft-mute activated for main channel
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
Reset condition
A Power on reset is invoked if the supply voltage is below than 3.5 V. After that the following
data is written automatically into the registers of all subaddresses:
MSB
LSB
1
1
1
1
1
1
1
0
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