M45PE16 Datasheet, PDF (29/45 Pages) STMicroelectronics – 16 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability and a 50 MHz SPI bus interface

M45PE16
Instructions
6.10
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t_SE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware
Protected is not executed.
Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Sector Erase (SE) instruction sequence
S
0123456789
29 30 31
C
Instruction
24 Bit Address
D
1. Address bits A23 to A21 are Don’t Care.
23 22
MSB
210
AI03751D
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