STM32F302XD Datasheet, PDF (28/168 Pages) STMicroelectronics – CRC calculation unit

Functional overview
STM32F302xD STM32F302xE
All I²C bus interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask). They also include programmable
analog and digital noise filters.
Table 6. Comparison of I²C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I²C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2,3) to wake up the MCU from Stop mode on address match.
The I²C interfaces can be served by the DMA controller.
Refer to Table 7 for the features available in I2C1, I2C2 and I2C3.
Table 7. STM32F302xD/E I²C implementation
I²C features⁽¹⁾
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
1. X = supported.
I2C2
X
X
X
X
X
X
X
X
I2C3
X
X
X
X
X
X
X
X
3.21
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F302xD/E devices have three embedded universal synchronous/asynchronous
receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbit/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
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