ST20-GP6 Datasheet, PDF (28/123 Pages) STMicroelectronics – GPS PROCESSOR

ST20-GP6
tion it returns to the trapped process via the tret (trap return) instruction. This reloads the values
saved in the trapped process structure and clears the trap flag in Status.
Note that when a trap handler is started, Areg, Breg and Creg are not saved. The trap handler
must save the Areg, Breg, Creg registers using stl (store local).
4.6.4 Trap instructions
Trap handlers and trapped processes can be set up and examined via the ldtraph, sttraph,
ldtrapped and sttrapped instructions. Table 4.7 describes the instructions that may be used when
dealing with traps.
Instruction Meaning
Use
ldtraph
load trap handler
Load the trap handler from memory to the trap handler descriptor.
sttraph
store trap handler
Store an existing trap handler descriptor to memory.
ldtrapped
load trapped
Load replacement trapped process status from memory.
sttrapped
store trapped
Store trapped process status to memory.
trapenb
trap enable
Enable traps.
trapdis
trap disable
Disable traps.
tret
trap return
Used to return from a trap handler.
causeerror cause error
Program can simulate the occurrence of an error.
Table 4.7 Instructions which may be used when dealing with traps
The first four instructions transfer data to/from the trap handler structures or trapped process struc-
tures from/to an area in memory. In these instructions Areg contains the trap group code (see
Table 4.3) and Breg points to the 4 word area of memory used as the source or destination of the
transfer. In addition Creg contains the priority of the handler to be installed/examined in the case of
ldtraph or sttraph. ldtrapped and sttrapped apply only to the current priority.
If the LoadTrap trap is enabled then ldtraph and ldtrapped do not perform the transfer but set the
LoadTrap trap flag. If the StoreTrap trap is enabled then sttraph and sttrapped do not perform the
transfer but set the StoreTrap trap flag.
The trap enable masks are encoded by an array of bits (see Table 4.4) which are set to indicate
which traps are enabled. This array of bits is stored in the lower half-word of the Enables register.
There is an Enables register for each priority. Traps are enabled or disabled by loading a mask into
Areg with bits set to indicate which traps are to be affected and the priority to affect in Breg. Exe-
cuting trapenb ORs the mask supplied in Areg with the trap enables mask in the Enables register
for the priority in Breg. Executing trapdis negates the mask supplied in Areg and ANDs it with the
trap enables mask in the Enables register for the priority in Breg. Both instructions return the pre-
vious value of the trap enables mask in Areg.
28/123