M41T93 Datasheet, PDF (28/49 Pages) STMicroelectronics – Serial SPI bus RTC with battery switchover

Clock operation
M41T93
3.7
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset
the timer within the specified period, the M41T93 sets the WDF (Watchdog Flag) and
generates a watchdog interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
Watchdog Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog
Register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function
until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog
Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled upon power-up and the Watchdog Register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE Bit is '0,' the watchdog function prevails and the frequency test function is denied.
3.8
Note:
8-Bit (countdown) timer
The Timer Value Register is an 8-bit binary countdown timer. It is enabled and disabled via
the Timer Control Register (11h) TE Bit. Other timer properties such as the source clock, or
interrupt generation are also selected in the Timer Control Register (see Table 7). For
accurate read back of the countdown value, the serial clock (SCL) must be operating at a
frequency of at least twice the selected timer clock.
The Timer Control register selects one of four source clock frequencies for the timer (4096,
64, 1, or 1/60Hz), and enables/disables the timer. The timer counts down from a software-
loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF)
Bit. The TF Bit can only be cleared by software. When asserted, the timer flag (TF) can also
be used to generate an interrupt (IRQ/FT/OUT) on the M41T93. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal
which follows the condition of TF. The Timer Interrupt/Timer Pulse (TI/TP) Bit is used to
control this mode selection. When reading the timer, the current countdown value is
returned.
Table 7. Timer control register map
Addr D7
D6
D5
D4
D3
D2
D1
D0
0Fh WDF AF1 AF2 BL
TF
OF
0
0
10h
Timer Countdown Value
11h TE TI/TP TIE
0
0
0
TD1 TD0
Function
Flags
Timer Value
Timer Control
Bit positions labeled with ‘0’ should always be written with logic '0.'
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