L6751 Datasheet, PDF (28/59 Pages) STMicroelectronics – Digitally controlled dual PWM for Intel VR12 and AMD SVI

Device configuration and pinstrapping tables
L6751
2. Transition threshold specified as delta with respect to previous step (DPM23 is wrt DPM12).
3. GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different
pinstrappings DPM1-3 and DPM4-6. See Table 12 for details.
4. Transition between 1Phase and 2Phase operation is set to 12 A but disabled in PS00h.
5. Dynamic phase management disabled, IC always working at maximum possible number of phases
except from when in >PS00h when transitioning between 1Phase and 2Phase at 12 A.
Table 12. GDC threshold definition⁽¹⁾
GDC1
GDC0
Threshold [A]⁽²⁾
1
N ⋅ 17A
1
0
N ⋅ 13A
1
N ⋅ 9A
0
0
GDC OFF
1. GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different
pinstrappings DPM1-3 and DPM4-6. See Table 11 for details.
2. N is the number of phase programmed for the multi-phase section.
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