STW4810 Datasheet, PDF (27/72 Pages) STMicroelectronics – Power Management for Multimedia Processors

STw4810
4 Functional description
Power control register at address 08h
Table 24. Power control register at address 08h
Address 1Fh
Address 1Eh
15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Not used
0
1
0
0
0
en_clk en_mo
squarer nitoring
en_
vana
not
used
EN
Bits
Name
4 en_clock_squarer
3 en_monitoring
2 en_vana
Value
Settings
0 Disabled
1 _{Enabled (sine wave signal input)}
0 Disabled / MONITORING = OFF
1 Enabled / VCORE & VIO_VMEM monitoring = ON
0 _{Disabled / VANA = OFF}
1 Enabled / VANA = ON
Default
0
1
1
Power control register at address 09h
Table 25. Power control register at address 09h
Address 1Fh
Address 1Eh
15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Not used
0
1
0
0
1
vaux_
sleep
not
used
vio_
vmem_
sleep
vcore_
sleep
EN
Bits
Name
4 vaux_sleep
2 vio_vmem_sleep
1 vcore_sleep
Value
Settings
When PWREN is low:
0 _{VAUX stays in normal mode}
1 VAUX goes in sleep mode (default)
When PWREN is low:
0 _{VIO_VMEM stays in normal mode}
1 VIO_VMEM goes in sleep mode
When PWREN is low:
0 _{VCORE stays in normal mode}
1 VCORE goes in sleep mode
Default
1
1
1
Rev3
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