PM0044 Datasheet, PDF (27/162 Pages) STMicroelectronics – STM8 CPU programming manual

PM0044
Pipelined execution
5.4.3
Pipeline with Call/Jump
In the example shown in Table 10, a branch is taken after the JP/CALL instruction, and the
fetched instruction(s) are lost (flush). New instructions must be fetched. 3 fetch sequences
are required to refill the pre-fetch buffer. The fetch start depends on the instruction being
executed.
For a JP instruction, the fetch can start during the first cycle of the "dummy" execution.
For the CALL instruction, it starts after the last cycle of the CALL execution.
Table 10. Example of pipeline with Call/Jump
Add.
Instruction
Decode
cycles
Execute
cycles
lgth
1
2
3
4
Cycle
56 7
8
9 10 11
0xC000
0xC001
INC A
JP label
1
1
1
DE
1
1
3 ^F1
DE
0xC004 LDW X,[$5432.w]
X
0xD010
label: NEG A
1
0xD011
CALL label2
1
0xD014 LDW X,[$5432.w]
X
0xD018 LDW X,[$7895.w]
X
0xE030
label2: INCW X
1
X
4
1
1
2
3
X
4
X
4
1
1
F₂
DE
F₁
DE E
F₂
F₃ FS
F₁ D E
Table 11.
Legend
Symbol/Color
F
FS
D
E
Definition
Fetch
Fetch stalled
Decode
Execute
5.4.4
Pipeline stalled
The decode stage can be stalled when the execution lasts more than one cycle.
The flush is due to the branch. Fetching the branch address is performed during the second
execution cycle of the BTJF instruction.
The Decode operation can also be stalled when the memory target is modified during the
previous instruction. In the example given in Table 12, the INCW Y instruction writes the X
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