UM0851 Datasheet, PDF (26/245 Pages) STMicroelectronics – SPEAr is a family of highly customizable ARM-based embedded

Platform section
UM0851
3.1.1
Hardware overview
SPEAr provides several GPTs acting as APB slaves. Each GPT consists of 2 independent
channels, each one made of a programmable 16-bit counter and a dedicated 8-bit timer
clock prescaler. The programmable 8-bit prescaler performs a clock division from 1 to 256.
Different input frequencies can be defined using SPEAr configuration registers.
The main features of the GPT module are listed below:
● Each timer module provides two independent channels with separate control, count,
clock prescaler and interrupt registers
● Each channel has 16-bit counter with a programmable timer interval
● Provides auto-reload or single-shot mode feature
The following table shows GPTs available on different SPEAr platforms:
Table 10. GPTs available on SPEAr
SPEAr600
1 GPT in each CPU subsystem
2 in application subsystem
1 in basic subsystem
SPEAr3xx
1 GPT in CPU subsystem
2 in basic subsystem
The following figure describes the GPT hardware interface.
Figure 2. GPT hardware interface
0,,
SYNTHESIZER
0,,
-(Z
!0"INTERFACE
'04#HANNEL
'04#HANNEL
-ATCH?)NT
-ATCH?)NT
3.1.2
The TIMER_CLK can be selected between a fixed 48 MHz source and PLL1, which is also
the source for the rest of the system. The PLL1 output also goes through a synthesizer
which can be programmed to derive the actual required operating GPT clock.
Software overview
SPEAr LSP provides proprietary software routines to allocate, program and use the general
purpose timer. This set of routines abstract the GPT hardware block and provide easy
kernel APIs to manage and control these timers. This layer does not provide any interface to
the user space.
The following figure explains the GPT framework as used by the kernel time keeping and
tick management subsystem. The GPT routines can also be directly used by user
modules/applications.
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Doc ID 16604 Rev 2