STA559BW Datasheet, PDF (26/67 Pages) STMicroelectronics – Selectable 32- to 192-kHz input sample rates

Register description
STA559BW
Table 19. Supported serial audio input formats for LSB-first
BICKI
SAI [3:0]
SAIFB
Interface Format
32 * fs
48 * fs
64 * fs
1100
1
1110
1
0100
1
0100
1
1000
1
1100
1
0001
1
0101
1
1001
1
1101
1
0010
1
0110
1
1010
1
1110
1
0000
1
0100
1
1000
1
1100
1
0001
1
0101
1
1001
1
1101
1
0010
1
0110
1
1010
1
1110
1
I²S 15-bit data
Left/right-justified 16-bit data
I²S 23-bit data
I²S 20-bit data
I²S 18-bit data
LSB first I²S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I²S 24-bit data
I²S 20-bit data
I²S 18-bit data
LSB first I²S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
To make the STA559BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
 N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,
where N depends on the settings in Table 12 on page 23.
 the PLL must be locked.
If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the
STA559BW immediately mutes the I²S PCM data out (provided to the processing block) and
it freezes any active processing task.
26/67
DocID18190 Rev 2