STA310 Datasheet, PDF (26/90 Pages) STMicroelectronics – 6+2-CH. MULTISTANDARD AUDIO DECODER

STA310
Figure 14. PCM Output Configurations
L
C
R
LS
RS
LFE
Configuration 0
Not used with Prologic
00 00 _{L -16dB}
0 0 _{C -16dB}
0 0 _{R -16dB}
00 0 0 00 00 0₀ 0₀ 0_{00 LS -16dB}
00 _{0 0 0 00 00 0}0 ₀00 _{RS -16dB}
LFE -6dB
-4dB
Configuration 2
L
L
C
C
R
R
LS
LS
RS
RS
Not
00000
u₀₀₀s₀₀₀e₀₀₀₀d₀000000₀₀
w₀₀₀000000000it₀₀h
Prologic
L
C
R
LS
RS
-18.5dB
LFE LFE
-8,5dB
SUB
L
L
C
C
R
R
LS
LS
RS
RS
Configuration 1
Not
0000
00^u00^{s000e0d0000000000w000000}0^it00^h00
Prologic
L
C
R
LS
RS
-18.5dB
Not used in
configuration 4
LFE -8,5dB
SUB
Configurations 3 and 4
5.2 PCM scaling
PCM scaling is needed for every decoding mode (AC3, Pro Logic, MPEG, PCM). It is applied at the end of the
filtering steps before PCM output, allowing maximum effective word width for most of the signal processing be-
fore.
Master volume (PCM_SCALE register) and balances (BAL_LR and BAL_SUR registers) are implemented for
PCM scaling.
5.3 Output quantization
For optimal results for 16/18/20-bit DACs, a quantization with rounding is applied together with the PCM scaling.
The sample value is multiplied by a rounding factor and rounded to 24 bits. The result is then left shifted (4/6/8)
for PCM output.
The output precision is selectable from the 16bits/word to 24 bits/word by configuring the field PREC in the reg-
ister PCMCONF.
5.4 Interface and output formats
The decoded audio data are output in serial PCM format.
The interface consists of the following signals
PCM_OUT0, 1, 2 PCM data, output,
SCLK
Bit clock (or serial clock), output,
LRCLK
Word clock (or Left/Right channel select clock), output,
PCMCLK
PCM clock, input or output (see <CrossRef><BlueHT>Clocks <BlueHT>on page 11 for details).
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