M34E04 Datasheet, PDF (26/32 Pages) STMicroelectronics – Enhanced ESD/latch-up protection

DC and AC parameters
M34E04
Symbol
Table 13. AC characteristics
V_CC < 2.2 V
Parameter
100 kHz
V_CC ≥ 2.2 V
400 kHz
1000 kHz Unit
Min. Max. Min. Max. Min. Max.
f_SCL
f_C
Clock frequency
10 100 10 400 10 1000 kHz
t_HIGH
t_CHCL
t_LOW ⁽¹⁾
t_CLCH
t_TIMEOUT ⁽²⁾
t_R ⁽³⁾
t_XH1XH2
t_F ⁽³⁾
t_QL1QL2
Clock pulse width high time
Clock pulse width low time
Detect clock low timeout
SDA rise time
SDA(out) fall time
4000 -
600
-
260
-
ns
4700
-
1300
-
500
-
ns
25
35
25
35
25
35 ms
-
1000 20 300
-
120 ns
-
300 20 300
-
120 ns
t_SU:DAT
t_DXCH Data in setup time
250
-
100
-
50
-
ns
t_HD:DI
t_CLDX Data in hold time
0
-
0
-
0
-
ns
t_HD:DAT
t_SU:STA ⁽⁴⁾
t_CLQX
t_CHDL
Data out hold time
Start condition setup time
200 3450 200 900 0 350 ns
4700 -
600
-
260
-
ns
t_HD:STA
t_DLCL Stop condition hold time
4000 -
600
-
260
-
ns
t_SU:STO
t_CHDH Stop condition setup time
4000 -
600
-
260
-
ns
t_BUF
t_DHDL
Time between Stop Condition and
next Start Condition
4700
-
1300
-
500
-
ns
t_W
t_POFF ⁽³⁾
t_INIT ⁽³⁾
Write time
-
5
-
5
-
5 ms
Time ensuring a Reset when V_CC
drops below V_PDR(min)
100
-
100
-
100
-
µs
Time from V_CC(min) to the first
command
0
-
0
-
0
-
µs
1. Initiate clock stretching, which is an optional SMBus bus feature.
2.
A timeout condition can only be ensured if SCL is driven low for
Standby mode and is ready to receive a new START condition. If
internal state remains unchanged.
tS_{TCIMLEOisUdTr(iMveanx)loowr}
longer;
for less
then
than
the M34E04 is
t_TIMEOUT(Min),
set
the
in
M34E04
3. Measured during characterization, not tested in production.
4. To avoid spurious START and STOP conditions, a minimum delay is placed between the falling edge of SCL and the falling
or rising edge of SDA.
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DocID023348 Rev 7