L4969URTR-E Datasheet, PDF (26/46 Pages) STMicroelectronics – System voltage regulator with fault tolerant low speed CAN transceiver

Functional description
L4969UR-E, L4969URD-E
3.10.3
The Address/command field starts with a 2-Bit start sequence consisting of ‘01’. Any other
sequence will lead to a protocol error signalled via the NINT. The address field is specifying
the register to be accessed. The SPI command flags allow in addition to the normal
read/write operation to clear the Interrupt flag register after read.
Datafield #1
Figure 10. Datafield #1
3.10.4
Datafield #1 contains either the lower 8 bits of a 12-bit frame or the complete byte of an 8-bit
transfer.
Note, that SOUT is always showing the content of the register currently accessed and not a
copy of SIN as during the address/command field.
Datafield #2/CRC
Figure 11. Datafield #2 / CRC
Datafield #2 contains either the upper four bits of a 12-bit frame or zeros in case of an 8-bit
transfer. This field is followed by a four bit CRC sequence that is calculated based upon the
polynom 0x11h (17 decimal). This sequence is simply the remainder of a polynomial
division performed on the data previously transferred. If the CRC appended to the SIN
sequence fails, any writing will be disabled and an error is signalled via NINT. Another
remainder is calculated on the SOUT stream and appended accordingly to allow the
application software to validate the correctness of incoming data. To aid evaluation, the CRC
checking can be turned off by writing arbitrary data with a valid CRC to address 15. CRC-
checking will be reenabled upon another operation of this kind (Toggled information).
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Doc ID 022587 Rev 2