AN4651 Datasheet, PDF (26/34 Pages) STMicroelectronics – STM32F3 series peripheral interconnect matrix

Interconnection descriptions
AN4651
3.12
From VREFINT to COMP
Besides to the DAC channel output, Vrefint (x1, x3/4, x1/2, x1/4) can be selected as
comparator inverting input using:
 COMPxINSEL bits in COMP_CSR register for STM32F37x devices,
 COMPxINMSEL bits in COMPx_CSR register for other STM32F3 devices.
3.13
From DAC to OPAMP
The DAC outputs are connected internally to OPAMP1, OPAMP3 and OPAMP4 non
inverting inputs as shown in Table 12.
Table 12. DAC output selection as OPAMP non inverting input
Non inverting input
OPAMP1
OPAMP3
OPAMP4
DAC channel
DAC1_CH2
DAC1_CH2
DAC1_CH1
3.14
From TIM to OPAMP
The selection of the OPAMP inverting and non-inverting inputs can be done automatically. In
this case the switch from one input to another is done automatically. This automatic switch is
triggered by the TIM1 CC6 output arriving on the OPAMP input multiplexers.
3.15
From TIM to TIM
Some STM32F3 timers are linked together internally for timer synchronization or chaining.
When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another timer configured in Slave Mode.
Depending on the selected synchronization mode, a configuration sequence is applied. This
is detailed in the Timer synchronization chapter in the reference manuals.
The slave mode selection is made using “SMS” bits in the selected timer slave mode control
register (TIMx_SMCR).
Table 13 presents the possible master/slave connections and indicates the internal trigger
connection in each case.
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