STM32F732XX Datasheet, PDF (25/122 Pages) STMicroelectronics – Dual mode Quad-SPI

STM32F732xx STM32F733xx
Functional overview
Figure 9. Power supply supervisor interconnection with internal reset OFF
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The V_DD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 10).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• V_BAT functionality is no more available and V_BAT pin should be connected to V_DD.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to V_SS.
Figure 10. PDR_ON control with internal reset OFF
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