STMPE812A Datasheet, PDF (24/53 Pages) STMicroelectronics – Integrated 4-wire resistive touchscreen controller, pen-down/real-time mode, fullyautonomous

Interrupt system
STMPE812A
ISR
7
TSC_ERR
0
6
TSC_RELEASE
0
5
4
3
P2
RESERVED
P1
0
0
0
Interrupt status register
2
1
0
P0
TSC_DATA
TSC_TOUCH
0
0
0
Address:
0x0A
Type:
R
Reset:
0x00
Description:
ISR register monitors the status of the interruption from a particular interrupt source
to the host. Regardless whether the INT_EN bits are enabled, the ISR bits are still
updated.
Writing to this register has no effect. Reading the register clears any asserted bit
Implementation: A shadow register MUST be used to ensure that Read+Clear action
DOES NOT clear up any bit that is not READ.
Note: Reading the Interrupt Enable Register also clears the ISR. It is recommended that no read operation on IER
to be executed during normal operation. IER should only be accessed during initialization.
[7] TSC_ERR
Error encountered in coordinate calculation in TSC, or touch detect not valid after sampling
[6] TSC_RELEASE:
Release of touch is detected
[5] P2
Port 2 activity (GPIO)
[4] RESERVED
[3] P1
Port 1 activity (GPIO/ADC/PWM)
[2] P0
Port 0 activity (GPIO)
[1] TSC_DATA
Touch data available. In internal timer and host-read controlled mode, this bit can only
be cleared after the data has been read by the host. In ACQ mode, this bit is cleared after the
data or the ISR is read by the host.
[0] TSC_TOUCH
Touch is detected.
(In PEN-DOWN interrupt mode, this bit is never cleared until pen is removed)
In PEN_DOWN interrupt mode, this status register will still be updated with event interrupt
status data, and cleared on read. However no interrupt will be issued based on this status
register.
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Doc ID 18225 Rev 4