STM32F407IGH6 Datasheet, PDF (24/185 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Description
STM32F405xx, STM32F407xx
The device also features an embedded programmable voltage detector (PVD) that monitors
the V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is
higher than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.
An external power supply supervisor should monitor V_DD and should maintain the device in
reset mode as long as V_DD is below a specified threshold. PDR_ON should be connected to
this external power supply supervisor. Refer to Figure 7: Power supply supervisor
interconnection with internal reset OFF.
Figure 7. Power supply supervisor interconnection with internal reset OFF
V_DD
External V_DD power supply supervisor
Ext. reset controller active when
V_DD < 1.7 V or 1.8 V ⁽¹⁾
PDR_ON
NRST
Application reset
signal (optional)
V_DD
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
MS31383V3
The V_DD specified threshold, below which the device must be maintained under reset, is
1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the
0 to 70 °C temperature range.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry is disabled
• The embedded programmable voltage detector (PVD) is disabled
• V_BAT functionality is no more available and V_BAT pin should be connected to V_DD
All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset
through the PDR_ON signal.
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DocID022152 Rev 4