M69AR048B Datasheet, PDF (24/29 Pages) STMicroelectronics – 32 Mbit (2Mb x16) 1.8V Asynchronous PSRAM

M69AR048B
Table 13. Standby Mode AC Characteristics
M69AR048B
Symbol
Alt.
Parameter
80, 85
Unit
Min
Max
t_CLEX
t_CSP
E2 Low Setup Time for Power-Down Entry
10
ns
t_EXCH
t_C2LP E2 Low Hold Time after Power-Down Entry
85
ns
t_EHEV ⁽¹⁾
t_CHH
E1 High Hold Time following E2 High after Power-Down Exit
(Deep Power-Down Mode only)
300
µs
t_CHEL ⁽²⁾
t_CHHP
E1 High Hold Time following E2 High after Power-Down Exit
(not in Deep Power-Down Mode)
1
µs
t_EHCH
t_CHS
E1 High Setup Time following E2 High after Power-Down Exit
0
µs
t_EHGL
t_CHOX E1 High to G Invalid Time for Standby Entry
10
ns
t_EHWL ⁽³⁾
t_CHWX E1 High to W Invalid Time for Standby Entry
10
ns
tτ ⁽⁴⁾
tτ
Input Transition Time
1
25
ns
Note: 1. Applicable also to Power-up.
2. Applicable when 4M, 8M or 16M Partial Power-Down mode is programmed
3. Some data might be written into any address location if tEHWL (min) is not satisfied.
4. The Input Transition Time (tτ ) at AC testing is 5ns as shown below. If actual tτ is longer than 5ns, it may violate AC specification
of some timing parameters.
Figure 23. Power-Down Programming AC Waveforms
A0-A20
E1
MSB ²
tAVAX
MSB ²
tAXAV
MSB ²
MSB ²
MSB ²
PDCADD3
tAXAVL ⁴
G
W
LB, UB
DQ0-DQ15
RDa
Cycle 1
RDa
Cycle 2
RDa
Cycle 3
00
Cycle 4
PDCD⁴
RDb
Cycle 5
Cycle 6
AI07225c
Note: E2 = High.
1. All address inputs must be High from Cycle 1 to Cycle 5.
2. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the
data programmed during the Power-Down Program sequence may be incorrect.
3. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data
programmed during the Power-Down Program sequence may be incorrect.
4. t_EHEL after the end of Cycle 6, the Power-Down Program is completed and the device returns to normal operation.
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