AN3422 Datasheet, PDF (24/52 Pages) STMicroelectronics – Migration of microcontroller applications from STM32F1 to STM32L1 series

Peripheral migration
AN3422
range 3 is selected (V_CORE = 1.2 V), the ADC is low speed (ADCCLK = 4 MHz,
250 Ksps).
– Clock for the digital interface (used for register read/write access). This clock is the
APB2 clock. The digital interface clock can be enabled/disabled through the
RCC_APB2ENR register (ADC1EN bit) and there is a bit to reset the ADC through
RCC_APB2RSTR[ADCRST] bit.
4.5
DMA
STM32F1 and STM32L1 series uses the same DMA controller fully compatible.
STM32F1 and STM32L1 series embeds two DMA controllers, each controller has up to 7
channels. Each channel is dedicated to managing memory access requests from one or
more peripherals. It has an arbiter for handling the priority between DMA requests.
The table below presents the correspondence between the DMA requests of the peripherals
in STM32F1 series and STM32L1 series.
Table 9. DMA request differences between STM32F1 series and STM32L1 series
Peripheral
DMA request
STM32F1 series
STM32L1 series
ADC1
ADC1
DMA1_Channel1
DMA1_Channel1
ADC2
ADC2
NA
NA
ADC3
ADC3
DMA2_Channel5
NA
DAC
DAC_Channel1 DMA2_Channel3 / DMA1_Channel3⁽¹⁾ DMA1_Channel2
DAC_Channel2 DMA2_Channel4 / DMA1_Channel4⁽¹⁾ DMA1_Channel3
SPI1
SPI2
SPI3
USART1
USART2
USART3
UART4
UART5
I2C1
SPI1_Rx
SPI1_Tx
SPI2_Rx
SPI2_Tx
SPI3_Rx
SPI3_Tx
USART1_Rx
USART1_Tx
USART2_Rx
USART2_Tx
USART3_Rx
USART3_Tx
UART4_Rx
UART4_Tx
UART5_Rx
UART5_Tx
I2C1_Rx
I2C1_Tx
DMA1_Channel2
DMA1_Channel3
DMA1_Channel4
DMA1_Channel5
DMA2_Channel1
DMA2_Channel2
DMA1_Channel5
DMA1_Channel4
DMA1_Channel6
DMA1_Channel7
DMA1_Channel3
DMA1_Channel2
DMA2_Channel3
DMA2_Channel5
DMA2_Channel4
DMA2_Channel1
DMA1_Channel7
DMA1_Channel6
DMA1_Channel2
DMA1_Channel3
DMA1_Channel4
DMA1_Channel5
DMA2_Channel1
DMA2_Channel2
DMA1_Channel5
DMA1_Channel4
DMA1_Channel6
DMA1_Channel7
DMA1_Channel3
DMA1_Channel2
DMA2_Channel3
DMA2_Channel5
DMA2_Channel2
DMA2_Channel1
DMA1_Channel7
DMA1_Channel6
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Doc ID 018976 Rev 2