STM32F405XX_12 Datasheet, PDF (23/180 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STM32F405xx, STM32F407xx
Description
2.2.13
2.2.14
Note:
2.2.15
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I²S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
Boot modes
At startup, boot pins are used to select one out of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
Power supply schemes
● V_DD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through V_DD pins.
● V_SSA, V_DDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL. V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.
● V_BAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V_DD is not present.
Refer to Figure 19: Power supply scheme for more details.
V_DD/V_DDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C
temperature range and an inverted reset signal is applied to PDR_ON.
Power supply supervisor
The power supply supervisor is enabled by holding PDR_ON high.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold level is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently. Three BOR thresholds are available through option bytes.
The device remains in reset mode when V_DD is below a specified threshold, V_POR/PDR or
V_BOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is higher
than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Doc ID 022152 Rev 3
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